The main barrier to the realization of a desirable Complementary Metal Oxide Semiconductor (CMOS) technology in compound semiconductors is the absence of a proper gate insulator structure and gate passivation layer that passivates the surface of a compound semiconductor structure reducing the interface state trap density and simultaneously provides for sufficient insulating properties that are necessary for low gate leakage currents in the picoamp to nanoamp range required by very large scale (VLSI) and ultra large scale (ULSI) integrated circuit technology. Field effect transistor (FETs) widely used in the III-V semiconductor industry typically employ metal gates placed directly on the compound semiconductor structure forming Schottky gate contacts that are have quiescent-state leakage currents exceeding many microamps. The use of non-insulated metal gates placed directly onto compound semiconductor technology further results in individual transistors and integrated circuits that have excessively high power dissipation, reduced transconductance, low threshold voltage, reduced logic swing and the inability to operate on a single power supply, and generally limited performance characteristics. The high magnitude of the quiescent leakage current limits the maximum integration of GaAs, InP, and GaN based devices to circuits of several hundred thousand transistors.
In contrast, conventional silicon technology has a very mature and useful complementary metal oxide semiconductor (CMOS) technology., In silicon CMOS technology an insulating layer may be formed at the silicon structure surface without the introduction or formation of an undue density of electronic traps in the combined silicon/SiO2 semiconductor structure. Typically the trap density in the silicon/SiO2 materials system observed before hydrogen passivation of any traps or defects is in the 1010–1011 cm−2/eV at the center of the band gap. Thus, the insulating layer formed at the silicon wafer surface may act as a passivating layer that occupies dangling bonds at the silicon surface, reduces the interface state trap density in the energy gap and protects the semiconductor surface from environmental contamination, non-planar oxidation or reaction of impurities and the associated formation of electronic traps. It is well know by those skilled in the art that the electronic traps that are observed midway between the conduction band and valence band are caused by the disruption of the crystal symmetry at a semiconductor surface. Thus, excessive intermixing or disruption of the semiconductor surface at the interface between the semiconductor structure and any upper layer or layers will introduce increased electronics traps into the semiconductor structure.
The simultaneous integration of many millions of transistors is possible at high integration densities using silicon CMOS technology. These ultra high integration densities and levels cannot be obtained using metal, Schottky-style gates that are not insulated from the compound semiconductor structure in compound semiconductor FETs. Thus Si CMOS technology offers significant advantages in terms of the low gate leakage of individual transistors, and circuit integration level and manufacturing cost.
However when compared to silicon technology, compound semiconductors such as GaAs, InP, and GaN exhibit faster and more optimized speed/power performance and efficiency. The market acceptance of these GaAs, InP, and GaN integrated circuit technologies remains low because of high gate leakage in compound semiconductor MESFETS and MOSFETs, the lack of ability to demonstrate high integration densities with low amounts of operating power, and higher manufacturing cost. Thus, silicon CMOS dominates the field of low power high performance analog and digital integrated circuitry, and circuits based upon GaAs, InP, GaN technologies cannot successfully penetrate this market.
What is needed is a compound semiconductor-passivation layer-insulator structure with an improved sharpness and abruptness at the semiconductor-passivation layer interface. What is needed are new and improved compound semiconductor field effect transistors (FET). What is needed is a compound semiconductor passivation layer that is conducting in a manner that allows the formation of a JFET-type junction adjacent to the channel. What is needed are p-type and n-type conducting passivation layers useful in JFET structure formation. What is needed are JFETs with a reduced gate leakage. What is also needed are new and improved compound semiconductor FETs using metal-oxide-semiconductor junctions (MOSFET). What is also needed are new and improved compound semiconductor MOSFETs using a self-aligned gate structure. What is also needed are new and improved self-aligned compound semiconductor MOSFETs using enhancement mode and depletion mode operation. What is also needed are new and improved self-aligned compound semiconductor MOSFETs with stable and reliable device operation. What is also needed are new and improved self-aligned compound semiconductor MOSFETs which enable optimum compound semiconductor device performance. What is also needed are new and improved self-aligned compound semiconductor MOSFETs with optimum efficiency and output power for RF and microwave applications. What is also needed are new and improved self-aligned compound semiconductor MOSFETs for use in complementary circuits and architectures. What is also needed are new and improved self-aligned compound semiconductor MOSFETs for low power/high performance complementary circuits and architectures. What is also needed are new and improved self-aligned compound semiconductor MOSFETs which offer the design flexibility of complementary architectures. What is also needed are new and improved self-aligned compound semiconductor MOSFETs which keep interconnection delays in ultra large scale integration under control. What is needed are new and useful complementary integrated circuits where each individual transistor has a leakage current approaching 10−12 amp. What is needed is a truly useful integrated circuit technology for GaAs, InP, and GaN that allows for the useful and economical operation of ULSI digital integrated circuits in compound semiconductors. What is needed are new and improved compound semiconductor MOSFET integrated circuits with very low net power dissipation. What is needed are new and improved compound semiconductor MOSFET devices with low gate leakage currents that may be integrated together to form ultra large scale integrated circuits that include millions of transistors. What is needed are new and improved complementary MOSFET devices and circuits in compound semiconductors that allow the direct use, transfer and application of silicon CMOS design that already exits in the art.
What is also needed are new and improved methods of fabrication of self-aligned compound semiconductor MOSFETs. What is also needed is new and improved methods of fabrication of self-aligned compound semiconductor MOSFETs that are compatible with established complementary GaAs heterostructure FETs technologies. What is also needed are new and improved compound semiconductor MOSFETs which are relatively easy to fabricate and use.